Low-Power Sequential Access Memory Design
نویسندگان
چکیده
This paper presents the design and evaluation of a sequential access memory (SAM) that provides low power and high performance by replacing address decoders with special locally-communicating sequencers. A test chip containing one 16x16-b SAM and one 64x16-b SAM (consisting of four 16x16-b banks) has been designed, fabricated, and evaluated using a 0.25-μm CMOS process. With a clock frequency of 40MHz at 1.2V, the measured worst-case read power dissipations for the 16x16-b SAM and the 64x16-b SAM are 344μW and 358μW respectively, demonstrating power dissipation that is mostly independent of SAM size.
منابع مشابه
Low Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
متن کاملEnergy Efficient Novel Design of Static Random Access Memory Memory Cell in Quantum-dot Cellular Automata Approach
This paper introduces a peculiar approach of designing Static Random Access Memory (SRAM) memory cell in Quantum-dot Cellular Automata (QCA) technique. The proposed design consists of one 3-input MG, one 5-input MG in addition to a (2×1) Multiplexer block utilizing the loop-based approach. The simulation results reveals the excellence of the proposed design. The proposed SRAM cell achieves 16% ...
متن کاملComparison and analysis of sequential circuits using different logic styles
In digital VLSI, power dissipation has become a prime constraint. Many design architecture and techniques have been developed to reduce power dissipation. In this paper implementation of sequential circuits such as D flip flop, PIPO shift register and RAM in Gate diffusion input (GDI) technique and its comparison with other logic styles is presented. This technique allows reduced power consumpt...
متن کاملDesign of a Low Power Magnetic Memory in the Presence of Process Variations
With the advancement in technology and shrinkage of transistor sizes, especially in technologies below 90 nm, one of the biggest problems of the conventional CMOS circuits is the high static power consumption due to increased leakage current. Spintronic devices, like magnetic tunnel junction (MTJ), thanks to their low power consumption, non-volatility, compatibility with CMOS transistors, and t...
متن کاملFPGA Implementation of a Hammerstein Based Digital Predistorter for Linearizing RF Power Amplifiers with Memory Effects
Power amplifiers (PAs) are inherently nonlinear elements and digital predistortion is a highly cost-effective approach to linearize them. Although most existing architectures assume that the PA has a memoryless nonlinearity, memory effects of the PAs in many applications ,such as wideband code-division multiple access (WCDMA) or orthogonal frequency-division multiplexing (OFDM), can no longer b...
متن کامل